A 27B Model at 30 Tokens a Second, No GPU — We Checked What That Requires

On 18 August 2026, Alibaba's XuanTie team announced day-zero support for Qwen3.8-27B on its C950 RISC-V processor: a 27-billion-parameter dense model decoding at more than 30 tokens per second, with a 1.9-second time to first token, on CPU cores alone. No GPU, no binary translation layer.

Thirty tokens a second is a little over twenty words a second — faster than you read. If that number holds on hardware you can buy, the floor for running a serious model at home stops being a graphics card.

Every outlet repeated those two figures. Nobody inverted them. So we did, and the arithmetic says something more interesting than either the hype or the dismissal.

Generating one token means reading every weight in the model once. So decode speed is a bandwidth statement, not a compute one: tokens per second is roughly memory bandwidth divided by the size of the weights. Turn that around and the claim becomes a hardware requirement.

For a 27B dense model, to sustain 30 tokens per second you need:

• ▸At Q8_0 — 28.7 GB of weights, so about 1,076 GB/s.
• ▸At Q6_K — 22.3 GB, about 835 GB/s.
• ▸At Q4_K_M — 15.2 GB, about 570 GB/s.
• ▸At INT4, which is the likely deployment precision — 13.5 GB, about 506 GB/s.
• ▸Even at a brutal 2-bit — 6.8 GB, still about 253 GB/s.

There is no quantisation aggressive enough to bring this into desktop territory. That is the whole story.

Put those requirements against hardware that exists:

• ▸Dual-channel DDR5-5600, which is what a normal PC has — about 90 GB/s, giving roughly 4.7 tokens per second on this model. Six times short.
• ▸An 8-channel DDR5 server — about 307 GB/s, roughly 16 tokens per second.
• ▸A 12-channel DDR5 platform — about 576 GB/s, roughly 30.3 tokens per second.
• ▸An Apple M5 Max — 614 GB/s, roughly 32 tokens per second.
• ▸An RTX 4090 — 1,008 GB/s, roughly 53 tokens per second.

Alibaba disclosed a 64-core target configuration. Sixty-four cores with server-class memory channels is not a desktop — it is a server. The claim is physically consistent, and it is consistent with a machine nobody has in a cupboard.

“Runs a 27B model without a GPU” is accurate. But the reason a GPU is normally required is not that it is a GPU — it is that it has fast memory attached. Take the GPU away and you still need the bandwidth. This result does not remove the requirement; it moves it into the CPU's memory system.

Which reframes what was actually demonstrated. Not “you no longer need a graphics card”, but “server memory bandwidth can substitute for one”. That is a real and interesting engineering result. It is not a consumer one.

The C950 exists as licensable RISC-V IP — a design other companies pay to integrate into their own silicon. There is no board, no price and no availability date, because there is no product. What was published is an internal result on a reference configuration.

Two further gaps worth naming:

• ▸Nobody outside Alibaba has reproduced it. Alibaba designed the instruction set extension, the core, the operator library and the model, then reported its own model running on its own core. That is not fraud, but it is a vendor benchmark and should be read as one.
• ▸No source reports the C950's memory bandwidth — the one number that would settle whether the result means what it appears to.
• ▸Only decode was measured. Prompt processing is a different workload, and a 1.9-second first token on a short prompt tells you nothing about what happens when you paste in 40,000 tokens of code.
• ▸The software ecosystem is CUDA-shaped. RISC-V inherits none of it for free.

Strip away the chip and the load-bearing news is the model. Qwen3.8-27B is Apache 2.0 with open weights, and it is a dense model, which makes the memory arithmetic straightforward — no mixture-of-experts routing to reason about. Three deployment paths exist today with published numbers behind them:

• ▸A 24 GB consumer card at Q4_K_M — about 18.7 GB needed at an 8K context, so it fits with room for the cache.
• ▸A server with the documented vLLM recipe, on hardware you already own.
• ▸A hosted endpoint, if you would rather not own any of this.

On the vision side, temper expectations. Independent evaluation puts Qwen3.8-27B 32nd of 34 models tested, with OCR called out as its weakest task — which is the vision job developers hand a model most often. It earns its reputation on text and code, not on the multimodal pitch.

One thing: a third party, unaffiliated with Alibaba, running this model on shipping silicon you can order, and publishing the decode speed, the prefill time and the memory bandwidth. Until that exists, treat every “no GPU” headline the same way — fit first, bandwidth second, source third.

The physics answer is yes: a decode loop needs capacity to hold the weights and bandwidth to sweep them, and nothing about that requires a graphics card. The purchasing answer is no, and will stay no until somebody ships a board. Those two answers are both true and people keep collapsing them into one.